GAL16V8D-15LP DIP20 
Datasheet
SPLD - Simple Programmable Logic Devices 5V 16 I/O, 15ns, 4.75 V - 5.25 V
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Description
The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified
APPLICATIONS
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
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Specifications:
| Manufacturer |
Lattice |
| Product Category |
SPLD - Programmable
Logic Devices |
| RoHS |
No |
| Logic Family |
GAL |
| Number of Macrocells |
8 |
| Maximum Operating Frequency |
62.5 MHz |
| Number of Programmable I/Os |
8 |
| Delay Time |
15 ns |
| Operating Supply Voltage |
5 V |
| Supply Current |
90 mA |
| Maximum Operating Temperature |
+ 75oC |
| Minimum Operating Temperature |
0oC |
| Package / Case |
PDIP-20 |
| Mounting Style |
Through Hole |
| Number of Product Terms per Macro |
8 |
| Packaging |
Tube |
| Factory Pack Quantity |
360 |
| Supply Voltage |
4.75 V - 5.25 V |
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