K4S561632E-TC75 SDRAM 256Mb E-die, 16M x 16, 166MHz (CL=3) 
DataSheet
Description
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications
Features
- JEDEC standard 3.3V power supply
- LVTTL compatible with multiplexed address
- Four banks operation
- MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
- All inputs are sampled at the positive going edge of the system clock.
- Burst read single-bit write operation
- DQM (x4,x8) & L(U)DQM (x16) for masking
- Auto & self refresh
- 64ms refresh period (8K Cycle)
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Parameters
| K4S561632E Key Parameters |
| Density |
256 Mb |
| Configuration |
4 x 4M x 16bits |
| Width |
x 16 |
| K4S561632E Other Features |
| Voltage |
3.3 V |
| Speed |
6.0ns (166MHz@CL=3)
7.5ns (133MHz@CL=3) |
| Refresh |
8K / 64ms |
| K4S561632E Packages and Pinouts |
| 54-pin TSSOP(II) |
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